An Error Compensated DCT Architecture with Booth Multiplier
نویسندگان
چکیده
In modern sciences and technologies, images have a broader scope due to growing importance of scientific visualization. Due to this image compression and manipulation is of major interest in research. In this paper, DCT architecture is proposed to deal with the truncation errors and to obtain a high throughput. Compensation architecture is done for the error due to truncation during multiplication to meet the PSNR requirements. An area efficiency and high speed is obtained by the radix 4 Booth multiplier comparing the works on multiplier based DCT. Thus an area of 20k gate counts and a PSNR of 40db is obtained for a grey scale image.
منابع مشابه
Error Compensated Fixed Width Modified Booth Multiplier for Multimedia Applications
Many multimedia and digital signal processing systems are desirable to maintain a fixed format and to allow little accuracy loss to output data. The objective of this paper is to design a fixed width modified booth multiplier with high error performance. And the need to derive an effective error compensation function that makes the error distribution more symmetric and centralized in the error ...
متن کاملOptimization of ECAT through DA-DCT
Discrete cosine transform (DCT) is a widely used tool in image and video compression applications. Recently, the high-throughput DCT designs have been adopted to fit the requirements of real-time application. Operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-speed discrete cosi...
متن کاملHigh Accuracy Fixed-width Booth Multipliers with Probabilistic Estimation Compensated Method
In this research, a probabilistic estimation compensation (PEC) method for fixed-width Booth multiplier is proposed. According to the probabilistic analysis for the truncation part,a formula is obtained to calculate the compensation value easily. In the application of long bit width, the PEC method is implemented by a simple compensation circuit without the exhaustive simulation to achieve a hi...
متن کاملVLSI Implementation of High Speed DCT Architecture for H.264 Video Codec Design
Field programmable gate arrays are ideally suited for the implementation of DCT based digital image compression. However, there are several issues that need to be solved. The Multiply-Accumulate Unit (MAC) is the main computational kernel in DIP architectures. The MAC unit establishes the power and the speed of the overall system; it always lies in the critical path. To develop high speed and l...
متن کاملDCT-based video frame-skipping transcoder
Due to high computational complexity and quality degradation introduced by conventional frame-skipping transcoders, a DCT-based video frame-skipping transcoder is proposed recently. However, the transcoding process of the motion compensated macroblocks in the DCT domain becomes the bottleneck since IDCT and DCT processes are required. In this paper, we propose a new architecture of the frame-sk...
متن کامل